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Murali Annavaram is a recipient of the 2008 IBM Faculty Awards

Alexander A. Sawchuk, Chair, Ming Hsieh Department of Electrical Engineering-Systems
August 13, 2008 —

I am very happy to announce that Murali Annavaram and Shri Narayanan of our Ming Hsieh Electrical Engineering faculty are recipients of 2008 IBM Faculty Awards. The IBM Faculty Awards are a competitive worldwide program intended to: foster collaboration between researchers at leading universities worldwide and those in IBM research and development; and promote courseware and curriculum innovation to stimulate growth in disciplines that are strategic to IBM. The awards consist of an unrestricted research grant, and winners are selected for their outstanding reputation and unusual promise for contributions in their field. Award candidates are nominated by an IBM employee with common interests who will serve as a liaison for the collaboration.

Murali Annavaram's work is concerned with novel processor architectures enabled by the 3D stacking of several separate chips that are combined to make an integrated single unit. As chip fabrication technologies continue to scale to smaller dimensions, unavoidable device manufacturing variations increasingly and adversely affect the predictability of circuit behavior leading to unreliable processors.
Traditionally component level fault tolerance is achieved by using some amount of redundancy. Using redundancy to cope with variability induced errors has one major drawback: the redundant component itself is prone to variation induced errors as redundant components are traditionally built on the same die as the primary processor. His research explores implementing redundant components and variability monitoring circuitry on a 3D stacked die in order to gain the benefits of monitoring, without its drawbacks. By using 3D stacking the redundant computation blocks can be built using a variation-resilient process technology that may be slower than the process technology used for building the primary processor. In this way the redundant components and the associated variability monitoring logic can be designed using an older process technology which is less susceptible to variability and without perturbing processor design.

By: Alexander A. Sawchuk, Chair, Ming Hsieh Department of Electrical Engineering-Systems