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1989 Tech Report

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CENG 89-01 Fault Tolerance and Reliability Analysis of Large-Scale Multicomputer Systems
by Walid A. Najjar
CENG 89-02 Parallel Computing with Optical Interconnects
by Mehrnoosh Mary Eshaghian
CENG 89-03 Test Generation Systems (TGS) User's Manual-Version 1.0
by Kuen-Jong Lee
CENG 89-04  
CENG 89-05 Detailed Analysis of Bridging Faults in CMOS Scan Registers
by Kuen-Jong Lee and Melvin A. Breuer
CENG 89-06 The EVE VLSI Management Environment
by Hamiden Afsarmanesh, Esther Brotoatmodjo, Kwang June Byeon
and Alice Parker
CENG -89-07 LARA: A Layout Accelerator based on Reduced Array Architecture
by C. P. RaviKumar and Sarma Sastry
CENG 89-08  
CENG -89-09 A Parallel Approach to Three-Layer Channel Routing
by C. P. RaviKumar and Sarma Sastry
CENG 89-10 SNAP: A Marker-Propagation Architecture for Knowledge Processing
by Dan Moldovan, Wing Lee, Changhwa Lin
CENG 89-11 SNAP: Simulation Results
by Dan Moldovan, Changhwa Lin
CENG 89-12 Text Understanding on SNAP
by Dan Moldovan and Ig-Tae Um
CENG 89-13 Reasoning on the Connection Machine
by Sang-Hwa Chung and Dan Moldovan
CENG 89-14 Control in Productions Systems with Multiple rule Firings
by Moldovan, Kuo and Cha, Steve Kuo, Dan Moldovan and Urula Schwultke
CENG 89-15 Parallel Asynchronous Algorithms for Discrete Data
by Michael Dubois and Adsin Uresin
CENG 89-16 An Asynchronous All Pairs Shortes Path Algorithm for Multiprocessors
by Uresin and Dubois
CENG 89-17 Worst Case Analysis of Asynchronous Iterative Algorithms
by Uresin and Dubois
CENG 89-18 Analytical Modeling of Data Sharing in Cache-Based Multiprocessors
by Wang and Dubois
CENG 89-19 Access Ordering and Coherence in shared Memory Multiprocessors
by Scheurich
CENG 89-20 Asynchronous Iterations with Bonded Delay
by Uresin and Dubois
CENG 89-21 Data Path Design Tradeoffs Using MABAL
by Kayhan Kucukcakar and Alice C. Parker
CENG 89-22 Fault Tolerant Multistage Interconnection Networks
by Yang and Silvester
CENG 89-23 High-Level Area Delay Prediction with Application to Behavioral Synthesis
by Rajiv Jain
CENG 89-24 Bandwidth Analysis of Message-Passing Networks
by Moldovan
CENG 89-25 Queueing Analysis of an ATM Switch with Multichannel Transmission
by Arthur Lin and John Silvester
CENG 89-26 Fixed-Node Routing and Architecture and its Performance in an ATM Switch
by Arthur Lin and John Silvester
CENG 89-27 The Macro Data Flow Simulator
by Namhoon Yoo and Jean-Luc Gaudiot
CENG 89-28 The USC Macro Data-Flow Assembly Language
by Jean-Luc gaudiot and Moez Ayed
CENG 89-29 The State of the Art in Parallel Production Systems
by Steven Kuo and Dan Moldovan
CENG 89-30 Implementation of Neural Networks on Massive Memory Organizations
by Manavendra Misra and V.K. Prasanna Kumar

CENG 89-31

Architecture Embeddings Designs a Simulation of an i860
Based Orthogonal Multiprocessor

by K. Hwang, D. Panda, C. Ching, S. Rao, S. Mahotra, H. Nair
CENG 89-32 Representing Temporal Information for Digital System Software
by John Granacki and Alice Parker
CENG 89-33 The Design of the SNAP Chip
by Wing Lee and Dan Moldovan
CENG 89-34 Parallel Classification for Knowledge Representation on SNAP
by Juntae Kim and Dan Moldovan
CENG 89-35 The Performance of an ATM Switch with Multichannel Transmission groups
by Arthur Lin and John Silvester
CENG 89-36 Self Routing Schemes in Parallel Memory Access
by Boppana and Raghavendra
CENG 89-37 Optimal Self Routing of Linear-Complement Permutations in Hypercubes
by Boppana and Raghavendra
CENG 89-38 Routing Games
by A. A. Economides and John Silvester
CENG 89-39 Priority Load Sharing: An Approach Using Stackalberg Games
by A.A. Economides and J.A. Silvester