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1993 Tech Reports

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CENG 93-01 A Direct Array Handling Technique for Non-strict and Parallel Accesses in a
Multithreaded Architecture

by Chinhyun Kim and Jean-Luc Gaudiot
CENG 93-02 The Detection and Elimination of Useless Misses in Multiprocessors
by Michel Dubois, Jonas Skeppstedt, Luvio Ricciulli, Krishnan Ramamurthy,
and Per Stenstrom
CENG 93-03 Estimating the Loss Probability in a Multiplexer Loaded with
Multipriority MMPP Streams

by Nelson L.S. Fonseca and John A. Silvester
CENG 93-04 Scalable Data Parallel Implementatons of object Recognition
using Geometric Hashing

by A. Khokhar, H. Kim, V. Prasanna, and C. Wang
CENG 93-05 A Discrete-Time Performance Model for Integrated Services ATM Multiplexers
by Shiouming Stanley Wang and John A. Silvester
CENG 93-06 Synthesis of Application-specific Multiprocessor Systems
by Shiouming Stanley Wang and John A. Silvester
CENG 93-07 HISS: A Prototype Program for Hierarchical Storage Synthesis
by Pravil Gupta and Alice Parker
CENG 93-08 An Efficient Partitioning Strategy for Pseudo-exhaustive Testing
by R. Srinivasan, S. Gupta, and M. Breuer
CENG 93-09  
CENG 93-10 FGMaps: Mapping for FPGAs using Function Decomposition
by Yung-Te Lai, Kuo-Rueih R. Pan and Massoud Pedram
CENG 93-11 FGILP: An Integer Linear Program Solver Based on Function Graphs
by Yung-Te Lai, Massoud Pedram and Sarma B.K. Vrudhula
CENG 93-12 Efficient Estimation of Dynamic Power Dissipation
by Chi-Ying Tsui, Massoud Pedram and Alvin M. Despain
CENG 93-13 Architecture and Routability Analysis for Row-Based FPGAs.
by Massoud Pedram, B. Nobandegani, and Bryan T. Press
CENG 97-14 Efficient Symbolic Simulation under the Extended Bounded Delay Model
for Transition Mode Timing Analysis

by Chihshun Ding and Massoud Pedram
CENG 93-15 Wire Delay Estimation
by Pravil Gupta and Alice Parker
CENG 93-16 PLA Delay Estmation
by Pravil Gupta and Alice Parker
CENG 93-17 Performance Analysis of Four Memory Consistency Models
for Multithreaded Multiprocessors

by Yong-Kim Chong and Kai Hwang
CENG 93-18 Hardwired Barriers for Fast Synchronization of Concurrent Processes
on Scalable Multiprocessors

by Shisheng Shang and Kai Hwang
CENG 93-19 Multicoloring of Grid-Structured PDE Solvers for Parallel Execution
on Multiprocessors

by H.C. Wang and Kai Hwang
CENG 93-20 Data Prefetching Effects on the Performance of Multithreaded

by Weighua Mao, Kai Hwang, and Rafeal H. Saavedra
CENG 93-21 Automatic Resolution of Pipeline Hazards in Pipeline Synthesis
of Instruction Set Processors

by Ing-Jer Huang and Alvin M. Despain
CENG 93-22 Advanced Silicon Compiler in Prolog
by Iksoo Pyo, Ching-long Su, Ing-jer Huang, Ricky Pan, Youngseon Koh,
Hsu-tsun Chen, Gino Cheng, Chi-ying Tsui, and Alvin M. Despain
CENG 93-23 Correctness of a Directory-Based Cache Coherence
Protocol: Early Experience

by Fong Pong and Michel Dubois
CENG 93-24 BEST: Behavioral Area-Delay Estimator
by Kayhan Kucukcakar and Alice C. Parker
CENG 93-25 Data-Driven and Multithreaded Architectures
by Jean-Luc Gaudiot and Chinhyun Kim
CENG 93-26 A Symbolic Approach for Checking Functional and Timing
by Chih-Tung Chen and Alice C. Parker
CENG 93-27  
CENG 93-28 Hardware/Software Tradeoffs in ADAM
by Jagannath Raghavendra and Alice Parker
CENG 93-29 Concurrent High-Level Synthesis with Floorplanning
by Jen-Pin Weng

 CENG 93-30

Loss Performance & Queue Length Statistics for Multimedia
Communication Systems

by Shiouming Stanley Wang and John A. Silvester
 CENG 93-31 Edge-Valued Binary-Decision Diagrams: Theory and Applications
by Yung-Te Lai, Massoud Pedram, and Sastry, Vrudhula
 CENG 93-32 Unified System Construction
by Alice C. Parker, Chih-Tung Chen & Pravil Gupta
 CENG 93-33 A Low Cost BIST Methodology & Associated Novel Test
Pattern Generator

by Sen Pin Lin, Sandeep K. Gupta and Melvin A. Breuer
 CENG 93-34 BIST Test Pattern Generators for Two-Pattern Testing-Theory
and Design Algorithms

by Chih-Ang Chen and Sandeep K. Gupta
 CENG 93-35 Modelling the Output Process of an ATM Multiplexer
with Markov Modulated Arrivals

by Nelson Fonseca and John Silvester
 CENG 93-36 Estimating End-to-End Delay in ATM Virtual Paths
by Estimating End-to-End Delay in ATM Virtual Paths 
CENG 93-37 High Level Interprocess Communication Primitives For A
Prolog to C-Parallel Translator

by Amaury de Cazanove
CENG 93-38 ProPart: A Process-Level Behavioral Partitioner
by Chih-Tung Chen and Alice C. Parker
CENG 93-39 SMASH: A Program for Scheduling Memory-Intensive Application
Specific Hardware

by Pravil Gupta and Alice Parker
CENG 93-40 Fuzzy Communications, Etc
by Chien-Ming Cheng and Kai Hwang
CENG 93-41 Compiler-Directed etc.
by Chien-Ming Cheng and Kai Hwang
CENG 93-42 Performance Results of The NAS Parallel Benchmarks in SISAL
by Hung-Yu Tseng and Jean-Luc Gaudiot
CENG 93-43 Exact & Approximate Methods for Calculating and Transition
Probabilities in FSM's

by CH-Ying Tsui, Massoud Pedram, Alvin Despain
CENG 93-44 Reduce Power Consumption of a High Performance Processor
Through Gray Code Addressing

by Ching-Long Su, Chi-Young Tsui, Alvin M. Despain
CENG 93-45 Cold Scheduling: Schedule Instructions for Less Bit Switches
by Ching-Long Su and Alvin M. Despain
 CENG 93-46 Branch with Masked Squashing in a Superpipelined Prolog Processor
by Ching-Long Su and Alvin M. Despain
 CENG 93-47 Logic Verification and Synthesis using Function Graphs
by Yung-Te Lai