Dr. Yuho Jin Projects Publications Contact Info Personal Page

Yuho Jin was a postdoctoral research associate in the Computer Engineering Division of the Ming Hsieh Department of Electrical Engineering at the University of Southern California and an NSF/CRA Computing Innovation Fellow since 2009. He received his PhD degree in Computer Engineering from the Department of Computer Science and Engineering at Texas A&M University. He participated in the PERCS project and carried out interconnect performance modeling at the IBM Austin Research Laboratory in 2007. He received his BS and MS degrees in the Department of Computer Science from KAIST in Korea. His research interests span on-chip networks design, memory system design, multicore architecture, and performance evaluation.

Now he is an assistant professor in Department of Computer Science at New Mexico State University since 2011. The new home page is found here.

Program Committee Member, Third International Workshop on Network on Chip Architectures (NoCArc), in conjunction with the 43rd IEEE/ACM International Symposium on Microarchitecture (MICRO-43), 2010

Program Committee Member, Fourth International Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), in conjunction with the 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA-16), 2010

Program Committee Member, Second International Workshop on Network on Chip Architectures (NoCArc), in conjunction with the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO-42), 2009

External Reviewer, ISCA, MICRO, HPCA, NOCS, ICCD, CAL, TPDS, TVLSI, JPDC

CIFellows Project: Communication-Aware Globally-Coordinated On-Chip Networks (poster)

• Thread Criticality Support in On-Chip Networks,
  Y. Jin, R. Wang, W. Choi, T. M. Pinkston
  Internatnional Workshop on Network on Chip Architectures (NoCArc), held in conjunction with International Symposium on Microarchitecture (MICRO-43), December 2010
  
• Adaptive Data Compression for Low-Power On-Chip Networks,
  Y. Jin, K. H. Yum, E. J. Kim,
  Book chapter entitled Low Power On-Chip Network Designs, Springer, 2010
  
• Integration of Admission, Congestion, and Peak Power Control in QoS-Aware Clusters,
  K. H. Yum, Y. Jin, E. J. Kim, and C. R. Das,
  Journal of Parallel and Distributed Computing (JPDC), Vol. 70, July 2010
  
• A Framework for End-to-end Simulation of High-Performance Computing Systems,
  W. E. Denzel, J. Li, P. Walker, Y. Jin,
  Simulation: Transactions of the Society for Modeling and Simulation International, 2010
  
• Design and Analysis of On-Chip Networks for Large-Scale Cache Systems,
  Y. Jin, E. J. Kim, K. H. Yum,
  IEEE Transactions on Computers (TC), Vol. 59, No.3, March 2010
  
• Recursive Patitioning Multicast: A Bandwidth-Efficient Routing for Networks-On-Chip,
  L. Wang, Y. Jin, H. Kim and E. J. Kim,
  International Symposium on Networks-On-Chip (NOCS), May 2009
  
• Adaptive Data Compression for High-Performance Low-Power On-Chip Networks,
  Y. Jin, K. H. Yum, E. J. Kim,
  International Symposium on Microarchitecture (MICRO), November 2008
  
• A Framework for End-to-end Simulation of High-Performance Computing Systems,
  W. E. Denzel, J. Li, P. Walker, Y. Jin,
  International Conference on Simulation Tools and Techniques for Communications, Networks, and Systems (SIMUTools), March 2008
  
• A Domain-Specific On-Chip Network Design for Large-Scale Cache Systems,
  Y. Jin, E. J. Kim, K. H. Yum,
  International Symposium on High-Performance Computer Architecture (HPCA), February 2007
  
• I/O Node Placement for Performance and Reliability in Torus Networks,
  T. Azeeze, H. Kim, Y. Jin, E. J. Kim,
  International Conference on Parallel and Distributed Computing and Systems (PDCS), November 2006
  
• Peak Power Control for a QoS Capable On-Chip Network,
  Y. Jin, E. J. Kim, K. H. Yum,
  International Conference on Parallel Processing (ICPP), June 2005
  IBM Austin Conference on Energy-Efficient Design (ACEED), March 2005