“Emulation of Neural Networks at Nanoscale,” Mary M. Eshaghian-Wilner, Aaron Friesz, Alex Khitun, Shiva Navab, Alice C. Parker, Kang L.Wang,  and Chongwu Zhou, accepted for publication, special issue of the Journal of Physics: Conference Series, 2007.

“Automated Design of Hierarchical Intranets,” by Sami Habib, Alice Parker, and Daniel Lee,  special issue of the Computer Communications Journal on Advances in Performance Evaluation of Computer and Telecommunications Networking,Vol. 25, No. 11-12, pp. 1065-1077, 2002.

 "A Suboptimal Heterogeneous Mapping," M. Eshaghian, A. Parker and Y-C Wu, Journal of High Performance Computing,  Vol. 3, No. 1, 1995, pp. 7-15.

``A Methodology and Design Tools to Support System-Level VLSI'', with K. Kucukcakar, IEEE Transactions on VLSI, 1995.

``Taking Thermal Considerations Into Account During High-Level Synthesis'', with J-P Weng, VLSI Design, Gordon and BreachPublishers, 1996.

``Synthesis of Application-Specific Multiprocessor Systems including Memory Components'', with S. Prakash, invited paper,special issue, Journal of VLSI Signal Processing, 1994.

``SOS: Synthesis of Application-Specific Heterogeneous Multiprocessor Systems'', with S. Prakash, Journal of Parallel and Distributed Computing, December 1992, Vol. 16, pp. 338-351.

``Predicting System-Level Area and Delay for Pipelined and Nonpipelined Designs'', with Rajiv Jain and Nohbyung Park, IEEETransactions on Computer-Aided Design, Vol. 11, No. 8, pp. 955-965,August 1992.

``The ADAM Design Planning Engine'', D. Knapp and A. Parker, IEEE Transactions on Computer-Aided Design, Vol. 10, #7, July 1991, pages 829-846.

``MABAL: A Software Package for Module and Bus Allocation'', with K. Kucukcakar, International Journal of Computer Aided VLSI Design, Vol. 2, No. 4, 1990, pp. 419-436.

``The High-Level Synthesis of Digital Systems'', with M. McFarland and R. Camposano, Proceedings of the IEEE, Feb. 1990, pp. 301-318.

``Techniques for Area Estimation of VLSI Layouts'', with F. Kurdahi, 34 pages, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 1989, pp. 81-92.

``Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications'', with N. Park, IEEE Transactions on Computer-Aided Design, Vol. 7, No. 3, March 1988,pp.356-370.

``Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems'', with N. Park, IEEE Transactions on Computers, Vol. 37, No. 6, June 1988, pp. 678-690.

``Automating the VLSI Design Process using Expert Systems and Silicon Compilation'', with S. Hayati, invited paper, Proceedingsof the IEEE, Vol. 75, No. 6, pp. 777-785, June 1987.

``Stochastic Models for Wireability Analysis of Gate Arrays,'' with S. Sastry, IEEE Transactions on Computer-Aided Design, Jan 1986, pp. 52-65.

``Automatic Synthesis of Digital Systems,'' invited paper, Design and Test, Sept., 1984, pp. 75-81.

``A Representation for Shape Based on Peaks and Ridges in the Difference of Low-Pass Transform,'' with James L. Crowley, IEEETransactions on Pattern Analysis and Machine Intelligence,March, 1984, pp. 156-170.

``An Abstract Model of Behavior for Hardware Descriptions,'' with Michael McFarland, IEEE Transactions on Computers, July, 1983, pp. 621-637.

``A Formal Method for the Specification, Analysis and Design of Register-Transfer Digital Logic,'' with L. Hafer, IEEE Transactions on Computer-Aided Design, Jan. 1983, pp. 846-853, reprinted in Advances in Circuits and Systems: Logic Synthesis for Integrated Circuit Design, ed: A. Richard Newton, IEEE Press, pp. 121-134, 1987.

`Synthesis of Hardware for the Control of Digital Systems,'' with A.W. Nagle and R. Cloutier, IEEE Transactions on Computer-Aided Design, Vol CAD-1, No. 4, Oct. 1982, pp. 201-212.

``Automated Synthesis of Digital Hardware,'' with L. Hafer. IEEE Transactions on Computers, Feb. 1982, pp. 93-109.

``A Design Methodology and Computer Aids for Digital VLSI Systems,'' with Director, Siewiorek and Thomas, IEEE Transactions on Circuits and Systems, vol. CAS-28, No. 7, July 1981, pp. 634-645, reprinted in Advances in Circuits and Systems: Computer-Aided Design of Very Large Scale Integrated Circuits, ed: Alberto L. Sangiovanni-Vincentelli, IEEE Press, pp. 86-96, 1987.

``SLIDE: An I/O Hardware Descriptive Language,'' with John Wallace. IEEE Transactions on Computers, June, 1981, pp. 423-439.

``The Automated Dictionary,'' with M. Fox and D. Bebel, invited paper, Computer, April 1980, pp. 35-48.

``A Bus System for the Military Computer Family,'' with William Burr, et. al., invited paper, Computer, April 1979, pp. 11-12.

 "System-Level Design", Alice C. Parker, Yosef Tirat-Gefen and Suhrid A. Wadekar, invited chapter in the IEEE/CRC VLSI Handbook, CRC Press, 1999, updated second edition  2006.

 "Critical Path Analysis," S. Dey, Yosef Tirat-Gefen, A.C. Parker, and M. Potkonjak, invited chapter in  Encyclopedia of Electrical Engineering, edited by J. Webster, John Wiley Inc., 1998.

``Synthesis in System Heterogeneous Computing'', Shiv Prakash, Alice C. Parker, and J-C DeSouza Batista, Heterogeneous Computing, Artech House, Mary Mehrnoosh Eshaghian, Editor, 1996.

``The ADAM Design Planning Engine'', A.C. Parker and D. Knapp, invited chapter Artificial Intelligence Approaches to Engineering Design, Morgan Kauffman, C. Tong and D. Sriram, Editors, 1992.

``Unified System Construction (U.S.C.)'', with K. Kucukcakar, S. Prakash and J. Weng, invited chapter, in  Trends in High-Level Synthesis W. Wolf and R. Camposano, Editors, Kluwer, June, 1991.

``Automating the VLSI Design Process using Expert Systems and Silicon Compilation'', A.C. Parker and S. Hayati, invited chapter, in Expert Systems, A Software Methodology for Modern Applications IEEE Press, Peter G. Raeth, Editor, 1990, pp. 101-109.

``An Object-Oriented Approach to VLSI CAD'', A.C. Parker, H. Afsarmanesh, D. Knapp and D. McLeod, invited chapter, Readings in Object-Oriented Databases Morgan Kaufmann Publishers, Stanley B. Zdonik and David Maier, Editors, pp. 607-618, 1989.

``Data Path Synthesis of Pipelined Designs: Theoretical Foundations'', N. Park, R. Jain and A.C. Parker invited chapter, Progress in Computer Aided VLSI Design, Volume III: Implementation Oct. 19, 1989, Ablex Publishing Corporation, George W. Zobrist, Editor.

``Interface and I/O Protocol Descriptions,'' A.C. Parker and N. Park, invited chapter, Advances in CAD for VLSI Vol. 7: Hardware Description Languages edited by R.Hartenstein, North Holland, pp. 111-136, 1985.

``Transfer Function Analysis of Picture Processing Operators,'' J. Crowley and A.C. Parker. In Issues in Digital Image Processing Haralick and Simon,
Sijthoff and Noordhof, The Netherlands, 1980, pp. 3-30.

“Emulation of Neural Networks on a Nano-scale Spin-Wave Architecture,” M M Eshaghian-Wilner, A Friesz, A Khitun, S Navab, A C Parker, Kang L.Wang, C Zhou, International Conference on Nanoscience and Technology, Basel, Switzerland, July-Aug., 2006.

“Towards a Nanoscale Artificial Cortex,” A. Parker, A. Friesz and A. Pakdaman, Conference on Computer Design + Computing in nanotechnology, Las Vegas, June, 2006.

"Automated Design of Hierarchical Intranets," S. Habib, A. C. Parker, and D. C. Lee, 2001 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, July, 2001, pp. 383-390.

"Computer-Aided System Integration for Data-Intensive Multimedia Applications", S. Habib and A. Parker, ACM Multimedia 2000, Nov., 2000, pp. 379-381.

"FREEDOM: Statistical   Behavioral Estimation of System Energy and Power," S.A. Wadekar, A. C. Parker and C.P. Ravikumar, in Proc. Eleventh   International Conference on VLSI Design, pp. 30-36, Jan. 1998.

"Accuracy Sensitive Word-Length Selection for Algorithm Optimization," S.A. Wadekar and A.C. Parker, in Proc. International Conf. on Circuit Design, pp. 54-61, Oct. 1998.

"Algorithm-Level Verification of Arithmetic-Intensive Application-Specific Hardware Designs for Computation Accuracy," S.A. Wadekar and A. C. Parker,  in Digest IEEE International High Level Design Validation and Test Workshop, pp. 80-87, Nov. 1998.

"An Evolutionary Approach to System Redesign", D.H. Heo, C.P. Ravikumar, and A. Parker, Proceedings of the 11th International Conference on VLSI Design, India, 1998, PP.359-362.

"Specification and Validation of System Level Designs" Diogenes C. Silva and Alice C. Parker, International Workshop on Logic and Architecture Synthesis - IWLAS '97, Grenoble, France, December 16-18 1997, pp. 255-264.

"Incorporating Imprecise Computation into System-level Design of Application-specific Heterogeneous Multiprocessors", 34th DAC proceedings, Yosef G. Tirat-Gefen, Diogenes C. Silva and Alice C. Parker, DAC'97 - Proceedings of the 34th. Design Automation Conference, Anaheim, CA June 9-13, 1997.

"Scheduling Problems in Distributed Multimedia Caching Applications," Sami Habib, Alice Parker, C.P. Ravikumar and Diogenes C. Silva, Proceedings of DMS '97 - Pacific Workshop on Distributed Multimedia Systems, Vancouver, Canada. July 23-25,1997

"Rapid Synthesis of Multi-Chip Systems", D.H. Heo, C.P. Ravikumar, and A. Parker, Proceedings of the 10th International Conference on VLSI Design, Hyderabad, India, Jan. 1997, pp.62-68.

"Synthesis of Optimal MCM-Based Systems," D.H. Heo, C.P. Ravikumar, and A. Parker, InterPACK'97, Kohala Coast, Island of Hawaii, USA, 1997. EEP-vol. 19-1,Advances in electronic packaging-1997,Vol.1, ACME 1997,PP.843-850.

"Storage Allocation and Scheduling Problem in Web Caching Applications, " S. Habib, C. P. Ravikumar and A. C. Parker, NLANR Web cache workshop, June 9-10, 1997, Boulder, Co. USA, Presented as a poster.

"MEGA: An approach to system-level design of application-specific heterogeneous multiprocessors", J.C. Batista and A C. Parker, Proceedings of the 5th Heterogeneous Computing Workshop, April 1996, also available as Tech. Report CENG 96-31, Dept. EE-Systems, USC.

``Optimal ILP-based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming'', with J.C. DeSouza-Batista and M. Potkonjak, Proceedings of the 32nd Design Automation Conference June, 1995.

``On Estimating the Resource Requirements of Heterogeneous Tasks'', with M. Eshaghian and Y-C Wu, Heterogeneous Computing Workshop April, 1995.

``Experience with Image Compression Chip Design using Unified System Construction Tools'', with P. Gupta, C. T. Chen, and J.C. DeSouza-Batista, Design automation Conference June, 1994.

``A Hybrid Numeric/Symbolic Program for Checking Functional and Timing Compatibility of Synthesized Designs'', with C. T. Chen and Alice C. Parker, Proceedings of the Seventh International Symposium on High-Level Synthesis Ontario, May 1994.

``SMASH: A Program for Scheduling Memory-Intensive Application Specific Hardware'', with P. Gupta and A. C. Parker, Proceedings of the Seventh International Symposium on High-Level Synthesis Ontario, May 1994.

``A Suboptimal Assignment of Application Tasks onto Heterogeneous Systems'', with J.S. DeSouza-Batista, M. Eshaghian, S. Prakash and Y-C Wu, Proceedings of the IEEE Computer Society Heterogeneous Computing Workshop April 1994.

``High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques'', with M. Potkonjak, S. Dey, Z. Iqbal, International Conference on Computer-Aided Design, ICCD, October 1993.

``Critical Path Minimization Using Retiming and Algebraic Speed-Up'', with Zia Iqbal, Miodrag Potkonjak, and Sujit Dey, in Proceedings 30th Design Automation Conference, Dallas June 1993, pp. 573-577.

``High Level Synthesis with Pin Constraints for Multiple-Chip Designs'', with Y.-H. Hung, in Proceedings of 29th Design Automation Conference ACM/IEEE, June, 1992.

``A Design Method for Optimal Synthesis of Application-Specific Heterogeneous Multiprocessor Systems'', with S. Prakash, in Proceedings IPPS '92 - Workshop on Heterogeneous Processing ACM/IEEE, March 1992.

``3D Scheduling: High-Level Synthesis with Floorplanning'', with J. Weng, in Proceedings of 28th Design Automation Conference ACM/IEEE, June, 1991.

``CHOP: A Constraint-Driven System-Level Partitioner'', with K. Kucukcakar, in Proceedings of 28th Design Automation Conference ACM/IEEE, June, 1991.

``Synthesis of Application-Specific Multiprocessor Architectures'', with S. Prakash, in Proceedings 28th Design Automation Conference ACM/IEEE, June, 1991.

``The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve'', with A. Hussain, P. Gupta and J. Weng, In Proceedings 28th Design Automation Conference ACM/IEEE, June, 1991.

``Data Path Tradeoffs using MABAL'', with K. Kucukcakar, Proceedings of the 27th Design Automation Conference, June, 1990, pp. 511-516.

``The EVE VLSI Information Management Environment'', with H. Afsarmanesh, E. Brotoatmodjo, and K.J. Byeon, Proceedings of the International Conference on Computer-Aided Design pp. 384-387, Nov. 1989.

``Experience with the ADAM Synthesis System'', with R. Jain, K. Kucukcakar, and M. J. Mlinar, Proceedings of the 26th Design Automation Conference ACM/IEEE, pp. 56-61, June 1989.

``Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions'', Proceedings of the 26th Design Automation Conference ACM/IEEE, pp. 75-80, June 1989.

``High Level Synthesis in the ADAM System'', et.al., Proceedings of the Second International Workshop of VLSI Design Bangalore, India,
December 1988.

``Area-Time Model for Synthesis of Non-Pipelined Designs'', with R. Jain and M. Mlinar, Proceedings of the 1988 International Conference on
Computer-Aided Design pp. 48-51, November 1988.

``Representation of Control and Timing Behavior with Applications to Interface Synthesis'', with S. Hayati and J. Granacki , Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors Rye Brook, New York, pp. 382-387, October 1988.

``The POTATO Chip Architecture: A Study in Tradeoffs for Signal Processing Chip design'', with B. Sharma, R. Jain, M. Breuer, C. Raghavendra and C.Y. Tseng, Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors Rye Brook, New York, pp.508-513, October 1988.

``Module Selection for Pipelined Synthesis'', with R. Jain and N. Park, Proceedings of the 25th Design Automation Conference pp. 542-547, June, 1988.

``Understanding System Specifications written in Natural Language'', with J. Granacki and Y. Arens, Proceedings of the 10th International Joint Conference on Artificial Intelligence August, 1987.

``Phrasal Analysis of Long Noun Sequences'', with Y. Arens and J. Granacki, Association for Computational Linguistics Annual Meeting July, 1987.

``PHRAN - Span: A Natural Language Interface for System Specifications'', with J. Granacki, Proceedings of the 24th ACM/IEEE Design Automation Conference pp. 416-422, June, 1987.

``REAL: A Program for Register Allocation'', with F. Kurdahi, Proceedings of the 24th ACM/IEEE Design Automation Conference June, 1987.

``Predicting Area - Time Tradeoffs for Pipelined Design'', with R. Jain and N. Park, Proceedings of the 24th ACM/IEEE Design Automation Conference pp. 35-41, June, 1987.

``Information Management for VLSI/CAD'', with H. Afsarmanesh, D. Knapp, and D. McLeod, Proceedings of the ICCD '86 IEEE International Conference on Computer Design VLSI IN Computers and Processors pp. 476-481, October 1986.

``A Design Utility Manager: The ADAM Planning Engine'', with D. Knapp, Proceedings of the 23rd Design Automation Conference pp. 48-54, June, 1986.

``SEHWA: 'A Program for Synthesis of Pipelines'', with N. Park, in 25 Years of Electronic Design Automation IEEE and ACM, June 1988, reprinted from Proceedings of the 23rd Design Automation Conference pp. 356-370, June, 1986.

``MAHA: A Program for Datapath Synthesis'', with J. Pizarro, M. Mlinar, Proceedings of the 23rd Design Automation Conference pp. 461-466, June, 1986.

``PLEST: A Program for Area Estimation of VLSI Integrated Circuits'', with F. Kurdahi, Proceedings of the 23rd Design Automation Conference pp. 467-473, June 1986.

``A Natural Language Interface for Specifying Digital Systems'', with J. Granacki, Proceedings of the First International Conference on Application of Artificial Intelligence to Engineering Problems Southampton England, April 15-18, 1986.

``A Unified Representation for Design Information'', with D. Knapp, Proceedings of the IFIP Conference on Hardware Description Languages, August, 1985.

`` An Extensible Object-Oriented Approach to Databases for VLSI/CAD'', with H. Afsarmanesh, D. Knapp and D. McLeod, Proceedings of the 11th International Conference on Very Large Data Bases Stockholm, pp. 164-166, August 21-23 1985.

``An Approach to Engineering Design Databases with Applications to VLSI/CAD'', with H. Afsarmanesh, D. McLeod, and D. Knapp, Proceedings of the International Conference on New Directions in Computing Technology Trondheim, Norway, August, 1985.

``The ADAM Advanced Design Automation System: Overview, Planner and Natural Language Interface'', with J. Granacki and D. Knapp, Proceedings of the 22nd Design Automation Conference, Las Vegas, pp. 727-730, June 1985.

``Synthesis of Optimal Clocking Schemes'', with N. Park, Proceedings of the 22nd Design Automation Conference Las Vegas, pp. 489-495, June 1985.

``A General Methodology for Synthesis and Verification of Register-Transfer Designs,'' with F. Kurdahi and M. Mlinar, Proceedings of the 21st Design Automation Conference, pp. 329-335, June, 1984.

``On the Relation Between Wire Length Distribution and Placement of Logic on Master Slice IC's,'' with S. Sastry, Proceedings of the 21st Design Automation Conference, pp. 710-711, June 1984.

``An Expert Synthesis System,'' with D. Knapp and J. Granacki, Proceedings of the International Conference on Computer-Aided Design, pp. 164-165, 1983.

``Procedural Layout: some Practical Experience for Production-Quality Integrated Circuits,'' with K. Wu and K. Conner, VLSI 1983 International Conference on VLSI Design. pp. 447-456, Aug. 1983.

``The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance,'' with J. Granacki, Proceedings of the 20th Design Automation Conference, pp. 419-424, June 1983.

``A Database System for Procedural VLSI Design,'' with K. Wu, Proceedings of 1983 Symposium on VLSI Technology Systems, and Applications, Taiwan, 1983.

``A Technique for Automatically Producing Optimized Digital Designs,'' with D. Dervos, MELECON '83, Mediterranean Electrotechnical Conference pp. B204-B205, May 1983 Proceedings.

``The Complexity of Two-Dimensional Compaction of VLSI Layouts,'' with S. Sastry, Proceedings of the 1982 International Conference on Circuits and Computers, Sept., 1982, pp. 402-406.

``Automating The Design of Testable Hardware,'' A. Parker and L. Hafer, Proceedings, First International VLSI Conference Edinburgh, August 1981, pp. 357-363.

``Digital System Simulation: Current Status and Future Trends,'' M. Breuer and A. Parker, Proceedings of the 18th Design Automation Conference June 1981, pp. 269-276.

``Algorithms for Multiple-Criterion Design of Microprogrammed Control Hardware,'' A. Nagle and A. Parker, Proceedings of the 18th Design Automation Conference, Nashville, June 1981, pp. 486-493.

``A Formal Method for the Specification, Analysis and Design of Register-Transfer Level Digital Logic,'' L. Hafer and A. Parker, in 25 Years of Electronic Design Automation IEEE and ACM, June 1988, reprinted from Proceedings of the18th Design Automation Conference, Nashville, June 9 1981, pp. 846-853.

``The SLIDE Simulator: A Facility for the Design and Analysis of Computer Interconnections,'' with A. Altman. Proceedings of the 17th Design Automation Conference, Minneapolis, pp. 148-155, June 1980.

``SLIDE: An I/O Hardware Descriptive Language,'' with John Wallace. Proceedings of 1979 International Symposium on Computer Hardware Descriptive Languages, pp. 423-439, October 1979.

``ISPS: A Retrospective View,'' with D. Thomas S. Crocker and R. Cattell. Proceedings of International Symposium on Computer Hardware Descriptive Languages, pp. 21-27, October 1979.

``The CMU Design Automation System: An Example of Automated Data Path Design,'' with Thomas, et. al. in 25 Years of Electronic Design Automation IEEE and ACM, June 1988, reprinted from Proceedings of the 16th Design Automation Conference, pp. 73-80, June 1979.

Proceedings of the 11th Annual Microprogramming Workshop, Editor, IEEE and ACM Publishers, November 1978.

``The Analysis, Synthesis and Evaluation of Local Measures for Discrimination and Segmentation of Textured Regions,'' with J. Crowley. Proceedings of the IEEE Pattern Recognition and Image Processing Conference, Chicago, pp. 372-378, June 1978.

``Register-Transfer Level Digital Design Automation: The Allocation Process,'' with L. Hafer, Proceedings of the 15th Design Automation Conference, pp. 213-219, June 1978.

``Description and Simulation of Microcode Execution,'' Proceedings of the Fifth Annual Computer Architecture Symposium, pp. 159-165, April 1978.

``Linear Analysis of Picture Processing Operators,'' with J. Crowley. Proceedings of the COMPCON, pp. 320-324, Spring 1978.

``Digital Interface Description,'' Proceedings of the COMPCON, Spring 1978.

``Envelope Control With an Optical Keyboard,'' with P. Dworak. Proceedings of the Second Annual Computer Music Conference, San Diego, October 1977.

``Hardware/Software Tradeoffs in a Variable Word Width, Variable Queue Length Buffer Memory,'' with A. Nagle. Proceedings of the 4th Annual Symposium on Computer Architecture, pp. 159-163, March 1977.

``The Design and Implementation of a Real-Time Sound Generation System,'' with others. Proceedings of the 4th Annual Symposium on Computer Architecture, pp. 153-158, March 1977.

``Educational and Industrial Applications of Register Transfer Modules,'' with D. Siewiorek. Euromicro, Proceedings of the Second Symposium on Microarchitecture, pp. 221-231, October 1976.

``Social Impacts of Advanced Domestic Load Managements Systems,'' with G. Morgan, S. Talukdar and D. Tuma. Frontiers of Power Technology Conference, pp. 153-158, October 1976.

``An Input Interface for the Real-Time Control of Musical Parameters,'' with P. Dworak. Proceedings of the First International Conference on Computer Music, MIT, pp. 221-231, October 1976.

``An Input Interface for a Real-Time Digital Sound Generation System,'' with Paul Dworak. Proceedings of the Third Annual Symposium on Computer Architecture, pp. 68-73, January 1976.

``A Language for the Specification of Digital Interfacing Problems,'' with James W. Gault. Proceedings of the 1975 International Symposium on Computer Hardware Descriptive Languages and Their Applications, New York, pp. 85-90, September 1975.

``Digital Analysis of Speech,'' presented at IEEE Region III Student Paper Competition, 1970, Gainesville, FL,