| University of Southern California | Carnegie Mellon University |
| University of Southern California Postdoctoral Researchers | Thesis or project topic | Current Position and Organization |
| C.P. Ravikumar | Unified System Construction | Leads the TI India Technical University at Texas Instruments, Bangalore, India |
| Nohbyung Park | ADAM Advanced Design AutoMation | Executive VP&CTO, R&D Center, Digital Media Network Business,Samsung Electronics Co., Ltd. |
| University of Southern California Ph.D. Students | ||
| Josef Gavriel (a.k.a. Yosef Gavriel Tirat-Gefen a.k.a. Jose Batista) | Theory and Practice in System-Level Design of Application-Specific Heterogeneous Multiprocessors | Castel Research and George Mason University |
| Chih-Tung Chen | Engineering Director, Qualcomm |
|
| Diogenes da Silva | A Comprehensive Framework for the Specification of Hardware/Software Systems | Assistant
Prof., Universidade Federal de Minas
Gerais, Belo Horizonte Brazil |
| John Granacki | Understanding Digital System Specifications Written in Natural Language | Director, Advanced Systems Division, Information Sciences Institute, USC |
| Pravil Gupta | VP and CTO of Selectica Inc. |
|
| Sami Habib | Synthesis and Optimization of Application-Specific Intranets | Assoc. Prof, U. of Kuwait |
| Sally Hayati | Director, Information Technology Department, The Aerospace Corporation | |
| Dong-Hyun Heo | Early System Architecture Optimization for Multi-Chip Systems | CAD Manager, Pulsent |
| Ivan Hom | A Methodology for Hardware/Software Co-Design of Embedded Systems | CAD Engineer, Transmeta |
| Yung-Hua Hung | High-Level Synthesis with Pin Constraints for Multiple-Chip Designs | Manager Transmission Technology Department, Industrial Technology Research Institute (ITRI) |
| Rajiv Jain | VP, Software Development Centre, AOL Bangalore |
|
| David Knapp | A Planning Model of the Design Process | Former Vice President and Chief Technology Officer, Get 2 Chip |
| Musaravakkam Samram. Krishnan | A layout Design Methodology for VLSI Structures |
|
| Kayhan Kucukcakar | System-Level Synthesis Techniques with Emphasis on Partitioning and Design Planning | Sr. R&D Manager, Synopsys |
| Fadi Kurdahi | Professor of Electrical Engineering, Univ. of California, Irvine | |
| Mitch Mlinar | Control Path/Data Path Tredeoffs in VLSI Design | R&D Group Director at Synopsys |
| Nohbyung Park | Synthesis of High-Speed Digital Systems | Executive VP&CTO, R&D Center, Digital Media Network Business,Samsung Electronics Co., Ltd. |
| Shiv Prakash | Synthesis of Application-Specific Multiprocessor Systems | Mentor Corp. |
| Jorge Siedel (a.k.a.Jorge Pizarro) | Aerospace Corporation |
|
| Sarma Vrudhula (a.k.a. Sarma Sastry) | Wiring Space Estimation of Master Slice ICs | Consortium
for Embedded Systems (CES) Chair Professor, Arizona State Univ. |
| Suhrid Wadekar | Accuracy Sensitive Word-Length Selection for Algorithm Optimization | formerly IBM, now law school |
| Jen-Pin Weng | Concurrent High-Level Synthesis with Floorplanning | Synopsys
Corp., Cadence? |
| University of Southern Calfornia M.S. Students | ||
| Charles Chao | ||
| Dimitrios Dervos | Aristotle U. of Thessaloniki, Dept. of Informatics, Greece | |
| Carnegie Mellon University Ph.D. Students | ||
| James Crowley | A Representation for Visual Information | Professor, Institut National Polytechnique de Grenoble |
| Louis Hafer | Professor, Simon Fraser Univ., Vancouver, BC | |
| Michael McFarland, SJ | President, Holy Cross Univ. | |
| Andrew Nagle | Automated Design of Digital-System Control Sequencers from Register-Transfer Specifications | Novell |
| Carnegie Mellon University M.S. Students | ||
| Arthur Altman | The SLIDE Simulator: A Design and Evaluation Tool for I/O and Interfacing Strategies | |
| Richard Blum | The Carnegie-Mellon University Computer Music System Hardware: The OEG, Oscillator and Envelope Generator | |
| Richard Cloutier | Control Allocation: The Automated Design of Digital Controllers | |
| Robert Colwell | Electronic Music | Chief IA32 ARchitect, Intel, independent consultant |
| Robert Cox | Image Processing Programs for the P5 Picture Processing Project | |
| Paul Ernst | ISPS Description of the Z8000 | |
| Grace Giras | A Distributed Bus Cluster Solution of Optimal Power Flow Implemented on CM* | |
| Ron Hensley | Pattern Recognition Applied to Music | |
| John T. Johl | Interfacing | |
| Charles Lo | The P.Display | |
| Edward J. Madera | Micro- Based Process I/O Scan and Control System | Westinghouse Corp.? |
| Neil Musicante | Optimal 3 Dimensional Display of Data Clusters for Pattern Recognition | |
| Mark Reich | ||
| Paul K. Rodman | Electronic Music | |
| John Wallace | The SLIDE Hardware Description Language | |
| Carnegie Mellon University Undergraduate Students | ||
| Lee Beckstrom | Encryption Hardware | |
| Michael Bergman | Micro Mouse Design | |
| Neil Bloomberg | Microprocessor-Based Digital Radio Communication - Noodle-One: A Microcomputer System | |
| Mark Carlotta | The CMU Computer Music System Envelope Generator | |
| George Conway | A Digital Circuit for Psychology Experiments | |
| Scott Craig | A Computer Textbook for Beginners | |
| Joan Cunningham | ISPS Descriptions | |
| Paul Ernst | ||
| Paul Green | An Analog Electronic Music Synthesizer | |
| Bob LaGatta | The Construction of a Motorola 6800 Microprocessor and Implementation of a Cross-Assembler | |
| Greg Lawson | The CMU Computer Music System - Front End Processor | |
| William Lyden |
The Construction of an Altair 8800 to RTM Interface, Hardware to Interface and Display Emulated Computer Registers, and A GLIDE (Generalized Language for Interface Description and Evaluation) Compiler |
|
| Barry Masel | Electronic Music | |
| Bob Mason | 8 Channel Recorder | |
| Michael Mehr | Feasibility of a Computer-Controllerd Circuits Laboratory | |
| Bill Morgart | Automatic Generation of Microcode | |
| Chris Moriondo | The CMU Computer Music System PDP-11 Interface | |
| Charles Squires | Construction of a Microprocessor System with Power Supply | |
| Mickey Tsao | A Virtual Image Memory | |
| John Wallace |
On Automatic
Verification
of SLIDE Descriptions |
Alice Parker | Electrical Engineering | University of Southern California
This page was last modified on April 21, 2003. | Copyright 1997, University of Southern California.
| This page represents the opinions of the author, and is not to be considered an official publication of the University of Southern California. |