CENG Technical Reports

1999 Tech Reports
CENG 99-01	Test Generation for Path-Delay Faults in Iterative Logic Arrays by Nabil Abdulrazzaq and Sandeep Gupta
CENG 99-02	Dynamic Power Management Based: A Continuous-Time Stochastic Approach by Qinru Qui, Qing Wu, and Masssoud Pedram
CENG 99-03	MCOMA: A Multithreaded COMA Architecture by Halima M. El Naga
CENG 99-04	Timing Analysis for Test Generation for Crosstalk-Induced Delay in Integrated Circuits by Wei-Yu Chen, Sandeep K. Gupta and Melvin a. breuer
CENG 99-05	LT-RTPG: A New Test Per Scan BIST TPG for Low Heat Dissipation by S. Wang and Sandeep K. Gupta
CENG 99-06	Optimizing Average-Case Performance in the Technology Mapping of Asynchronous Circuits by Wei-Chun Chou
CENG 99-07	Benchmarking of HPC System by Dongsoo Kang, Henry W. Park, Jinwoo Suh, Viktor K. Prasanna and Sharad N. Gavali
CENG 99-08	An Efficient Algorith for Large Scale Metrics Transposition by Jinwoo Suh, Santosh Narayanan, and Viktor k. Prasanna
CENG 99-09	Design & Perormance of SMMPs with Asynchronous Caches by Fong Pong, Michel Dubois, and Ken Lee
CENG 99-10	Performance Analysis of Asynchronous Circuits and Systems by Aiguo Xie

1998 Tech Reports
CENG 98-01	A Methodology for transforming Memory Tests for In-system Testing of Direct Mapped Cache Tags by Sultan Al-Harbi and Sandeep Gupta
CENG 98-02	Design and Performance of the Software-Controlled Coma by Adian Moga
CENG 98-03	Generalized Input Reduction BIST TPG for Cluster Interconnection Test at Board Levels by C-H Chiang and Saneep Gupta
CENG 98-04	Codex-dp: Co-design of Communicating Systems Using Dynamic Programming by Jui-Ming Chang and Massoud Pedram
CENG 98-05	Design of Application Software for Embedded Signal Processing by Wenheng Liu and Viktor K. Prasanna
CENG 98-06	T-Robust Testing for Delay Faults by Suriya Natalrajan, Sandeep Gupta and Melvin Breuer
CENG 99-07	A New Path-Oriented Effect-Cause Methodology to Diagnose Delay Failures by Yuan-Chieh Hsu and Sandeep K. Gupta
CENG 98-08	Options for Dynamic Address translation in COMAs by Xiaogang Qui and Michel Dubois
CENG 98-09	Parallel Implementation of a Class of Adaptive Signal Processing Applications by Myungho Lee and Viktor K. Prasanna
CENG 98-10	Synthesis of Area-Efficient and High-Throughput Rate Data Format Converters by Jongwoo Bae and Viktor K. Prasanna
CENG 98-11	Cycle-Accurate Macro Models for RT-Level Power Analysis by Qing Wu and Massoud Pedram
CENG 98-12
CENG 98-13
CENG 98-14
CENG 98-15
CENG 98-16	Automatic Array Partitioning and Distributed Array Compilation for Efficient Communication by Hung-Yu Tseng
CENG 98-17	Analysis of Variance in Micropipelines by Aiguo Xie and Peter Beerel
CENG 98-18
CENG 98-19	Micro Processor Power Estimation Using Profile Drive Program Synthesis by Cheng-Ta Hsieh and Massoud Pedram
CENG 98-20	Anaysis and Implementation of Optoelectronic Network Routers by Mongkol Raksapatcharawong
CENG 98-21	Logical Physical Co-Design for Deep Submicron Digital Circuits by Amir H. Salek. Jinan Lou and Massoud Pedram
CENG 98-22	Efficient Algorithms for Block-Cyclic Array Redistribution between Processor Sets by Neugsoo Park and Viktor K. Prasanna
CENG 98-23	A Dynamic Resource Allocation and Measurement-Based Call Admission Control Algorithm for Integrated Service Networks by Tien Chien Yu and John Silvester
CENG 98-24	Interaction between Multimedia and Traditional (FTP/WEB) Applications: An Experimental Performance Study by Gurvinder Singh and John Silvester
CENG 98-25	Assisted Execution by Michel Dubois and Yong Ho Song
CENG 98-26	Studies on the Impact of Long-term Correlation on Computer Network Performance: Part I Link-Layer Modeling by Hany D. Alsaialy and John Silvester
CENG 98-27	Studies on the Impact of Long-term Correlation on Computer Network Performance: Part II Link-Layer Modeling by Hany D. Alsaialy and John Silvester
CENG 98-28	Accuracy Sensititive Word-Length Selection for Algorithm Optimization by Suhrid Ashok Wadekar
CENG 98-29	Probabilistic Analysis of Power Dissipation in VLSI Systems by Radu Marculescu
CENG 98-30	Studies on the Impact of Long-Term Correlation on Computer Network Performance by Hany D. Alsaialy
CENG 98-31	Optimization of BIST Resources During High-Level Systems by Ishwar Parulkar

1997 Tech Reports
CENG 97-01	Implementation of Deadlock Detection in a Simulated Interconnection Network Environment by Sugath Warnakulasuriya and Timothy Pinkston
CENG 97-02	Memory Organizations in Hybrid DSM: A Performance Comparison by Adrian Moga, Alain Gefflaut, and Michel Dubois
CENG 97-03	Hardware vs. Software Implementation of COMA by Adrian Moga, Alain Gefflaut, and Michel Dubois
CENG 97-04	Hybrid Compiler/Hardware Prefetching for Multiprocessors Using Low-Overhead Cache Miss Traps by Jonas Skeppstedt and Michel Dubois
CENG 97-05
CENG 97-06	Variations in Electrical Values and Their Ramifications on Correct Circuit Operation by S. Natarajan, M.A. Breuer and S. K. Gupta
CENG 97-07	Vector Compaction Using Hierarchical Markov Models by R. Marculescu, D. Marculescu and M. Pedram
CENG 97-08	FSM Analysis Using High-Order Markov Models by R. Marculescu, D. Marculescu and M. Pedram
CENG 97-09	Statistical Estimation of Distribution of Power Dissipation in VLSI Circuits by Chih-Shun Ding and M. Pedram
CENG 97-10	Efficient Algorithms for Block-Cyclic Redistribution of Arrays by Young Won Lim, Prashanth B. Bhat and Viktor K. Prasanna
CENG 97-11	The Effectiveness of SRAM Network Caches in Clustered DSMs by Young Won Lim, Prashanth B. Bhat and Viktor K. Prasanna
CENG 97-12	Analytic Models for Crosstalk Delay and Pulse Analysis for Non-Ideal Inputs by Weiyu Chen, Melvin Breuer and Sandeep Gupta
CENG 97-13	Early System Architecture Optimization for Multi-Chip Systems by Dong-Hyun Heo
CENG 97-14	Improving the Quality of Safe BDD Minimization Using Don't Cares by Youngpyo Hong and Peter Beerel
CENG 97-15	Minimizing BIST Resource Requirements of Data Paths Using Redundancy by Iswar Parulkar, Sandeep Gupta, and Melvin Breuer
CENG 97-16	An Adaptive Multi-Class Call Admission Control for Multimedia Wireless Networks by Ebrahim Abdulrahman Ismail
CENG 97-17	BIST TPG for Faults in Backplane Interconnect by Chen-Huan Chiang and Sandeep Gupta
CENG 97-18	Portable Implementation of Real-Time Signal Processing Benchmarks on HPC Platforms by Jinwoo Suh and Viktor K. Prasanna
CENG 97-19	Steady-State Probability Estimation in FSMs Considering High-Order Temporal Effects by D. Marculescu, R. Marculescu, and M. Pedram
CENG 97-20	Efficient State Classification of Finite Markov Chains by Aiguo Xie and Peter A. Beerel
CENG 97-21	Accelerating Markovian Analysis of Asynchronous Systems Using String-based State Compression by Aiguo Xie and Peter A. Beerel
CENG 97-22	Fanout Optimization under a Submicron Transistor-Level Delay Model by Pasquale Cocchini and Massoud Pedram
CENG 97-23	EZDB: A Framework for Easy Evaluations of Commercial Applications by Kangwoo Lee, Jigar Thakkar, and Michel Dubois
CENG 97-24	Empirical Performance Modeling of Multiprocessors Based on Data-Sharing Analysis by Kangwoo Lee
CENG 97-25	Efficient Reachability Analysis of Large Finite State Machines Using Don't Care-Based BDD Minimization by Youpyo Hong and Peter A. Beerel
CENG 97-26	The Physical Design of RPM by Jaeheon Jeong, Yongho Song, and Michel Dubois
CENG 97-27	Implementation of a CC-NUMA on RPM by Jaeheon Jeong, Yongho Song, Adrian Moga and Michel Dubois
CENG 97-28	Rapid Hardware Prototyping on RPM-2: Methodology and Experience by Michel Dubois, Alain Gefflaut, Jaeheong Jeong, Adrian Moga, and Koray Oner
CENG 97-29	Theory and Practice in Siptem-Level Design of Application-Specific Heterogeneous Multi-processors by Yosef Howriel Tirat-Hefen

1996 Tech Reports
CENG 96-01	Modeling Survey: The Relationship between Environments, Services, and Network Performance in Wireless by Te-Kai Liu and John A. Silvester
CENG 96-02	Retransmission Control and Fairness Issue in Mobile Slotted ALOHA Networks with Fading and Near-far Effect by Te-Kai Liu and John A. Silvester, and Andreas Polydoros
CENG 96-03	Design and Evaluation of a Software-Controlled COMA by Alain Gefflaut, Adrian Moga, Jaeheon Jeong, and Michel Dubois
CENG 96-04	Computing ODCs and function Minimization Targeting Low Power by Sasan Iman and Massoud Pedram
CENG 96-05	Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming by Jaewon Oh, Iksoo Pyo and Massoud Pedram
CENG 96-06	Estimating BIST Resources in High-level Synthesis by Ishwar Parulkar, Sandeep K. Gupta and Melvin A. Breuer
CENG 96-07	A Satisfiability-Based Test Generator for path Delay Faults in Combinational Circuits by Chih-Ang Chen and Sandeep Gupta
CENG 96-08	A Framework for Coarse Grain Parallel Execution of Functional Program by Dae-Kyun Yoon
CENG 96-09	Bounds on Pseudo-Exhaustive Test Lengths by Rajagopalan Srinivasan, Sandeep K. Gupta, and Melvin A. Breuer
CENG 96-10	Stateful Computations in Functional Languages by Yung-Syau Chen
CENG 96-11	Statistical Sampling for VLSI Circuits by Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu and Massoud Pedram
CENG 96-12	Multi-level Logic Synthesis Based on Function Decomposition by Kuo-Rueih Ricky Pan
CENG 96-13	How to Minimize Energy Using Multiple Supply Voltages by JuiMing Chang and Massoud Pedram
CENG 96-14	Vector Compaction Using Dynamic Markov Models by Radu & Diana Marculescu and Massoud Pedram
CENG 96-15	Performance Modeling and Design Trade-offs of Wireless Communication Networks with Heterogeneous by Te-Kai Liu
CENG 96-16	Constrained Sequence Generation Using Schochastic Sequential Machines by D. Marculescu, R. Marculescu and M. Pedram
CENG 96-17	A Trace-Driven Simulation of an ATM Queueing System by Gilberto Mayor and John Silvester
CENG 96-18	An ATM Queueing System with Long-Range Dependent Traffic: Providing QoS Guarantees by Gilberto Mayor and John Silvester
CENG 96-19	High Performance Parallel Logic programming on Distributed Shared Memory Multiprocessors by Hiecheol Kim
CENG 96-20	Test Generation 7 Embedding for Built-in Self-Test by C. A. Chen
CENG 96-21
CENG 96-22	ATPG for Heat Dissipation Minimization for Scan Testing by Seongmoon Wang and Sandeep K. Gupta
CENG 96-23	System-Level Estimation of Energy and Power by Surid Wadekar and Alice Parker
CENG 96-24	Statistical Design of Macro-models for RT-Level Power by Qing Wu and Massoud Pedram
CENG 96-25	Rapid synthesis of Multi-chip Systems by Dong Hyun Heo, C. P. Ravikumar, and Alice Parker
CENG 96-26	Versatile Multichip Digital System Architecture Synthesis Tools by Dong Hyun Heo, C. P. Ravikumar, and Alice Parker
CENG 96-27	Generalized Input Reduction BIST for Interconnection faults via Boundary Scan at the board Level by Chen-Huan Chiang and Sandeep Gupta
CENG 96-28	High Quality Robust Tests for Path Delay Faults by Liang-Chi Chen, Sandeep Gupta, Melvin A. Breuer
CENG 96-29	Optimal Synthesis of Application Specific Heterogeneous Multiprocessors by Y.G. Tirat-Geen and Alice Parker
CENG 96-30	Optimal ILP-based Approach for Throughput Optimization Using Algorithm/Architecture Matching and retiming by Y.G. Tirat-Geen and Alice Parker
CENG 96-31	MESGA: An Approach to System-Level Design of Application-Specific Heterogeneous by Y.G. Tirat-Geen and Alice Parker
CENG 96-32	Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors by Y.G. Tirat-Geen and Alice Parker
CENG 96-33	System-Level Design of Application-Specific Heterogeneous Multiprocessors in the presence of Uncertainty by Y.G. Tirat-Geen and Alice Parker
CENG 96-34	Turn Selection Enhancements to Deadlock Recovery Algorithms by Timothy M. Pinkston, Joseph Borsody and William Kostes
CENG 96-35	Parallelism Control in Multithreaded Multiprocessors by Namhoon Yoo
CENG 96-36	Automatic Code Partitioning for Distributed Memory Multiprocessors (DMMs) by Moez Ayed
CENG 96-37	An Efficient Heuristic for Code Partitioning by Moez Ayed and Jean-Luc Gaudiot

1995 Tech Reports
CENG 95-01	Nomadic Threads: A Runtime Approach for Managing Remote Memory Accesses in Multiprocessors by Stephen Jenks and Jean-Luc Gaudiot
CENG 95-02	Data Path Allocation Techniquest for High-Level Synthesis of Low BIST Area Overhead Designs by Ishwar Parulkar, Sandeep Gupta and Melvin Breuer
CENG 95-03	Power Efficient Register Assignment by Jui-Ming Chang and Massoud Pedram
CENG 95-04	Switching Activity Estimation Based on Conditional Independence by Radu Marculescu, Diana Marculescu and Massoud Pedram
CENG 95-05	Effects of Asynchronism on the Convergence Rate of A Class of iTERATIONS by Aydin Uresin and Michel Dubois
CENG 95-06	Performance of Asynchronous Linear Iterations With Random Delays by Adrian C. Moga and Michel Dubois
CENG 95-07	Implementation And Performance Of Asynchronous And Synchronous Data Classification Algorithms by Adrian C. Moga and Michel Dubois
CENG 95-08	ASPEED Cache Coherence Protocol For An Optical Multi-Access Interconnect Architecture by Joon-Ho Ha and Timothy M. Pinkston
CENG 95-09
CENG 95-10	Parallel HO-PD Benchmark on the IBM SP2 by M. Arakawa, Z. Xu and K. Hwang
CENG 95-11	Parallel APT Benchmark on the IBM SP2 by M. Arakawa, Z. Xu and K. Hwang
CENG 95-12	Parallel General Benchmark on the IBM SP2 by M. Arakawa, Z. Xu and K. Hwang
CENG 95-13	Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing by Kai Hwang and Zhiewei Xu
CENG 95-14	Modeling Communication Overheard: MPI and MPL Performance on the IB SP2 Multicomputer by Kai Hwang and Zhiewei Xu
CENG 95-15	Early Pediction of MPP Performance of Workload and Overhead Quantification A Case Study of the IBM SP2 System by Kai Hwang and Zhiewei Xu
CENG 95-16	Power Efficient Module Allocation and Binding by Jui-Ming Chang and Massoud Pedram
CENG 95-17	Normalized NETLENGTHS: A Measure of Routing Cost for Logic Synthesis by H. Vaishnav and Massoud Pedram
CENG 95-18	Delay Optimal Partitioning Targeting Low Power VLSI Circuits by Hirendu Vaishnav and Massoud Pedram
CENG 95-19	Simulation of the Communication Libraries of the CM-5 on UNIX Workstations by Nicolas Guerin and J-L Gaudiot
CENG 95-20	Optimizatin of Post-Layout Area, Delay and Power Dissipation by Hirendu Vaishnav
CENG 95-21	Deadlock-Free Adaptive Wormhole Routing with Disha Concurrent by Anjan K. V., Timothy M. Pinkston, Jose Duato
CENG 95-22	Modeling Free-Space Optical k-ary n-cube Wormhole Networks by Mongkol Raksapatcharawong and Timothy M. Pinkston
CENG 95-23	Multiprocessor Emulation with RPM: Early Experience by Michel Dubois, Allain Gefflaut, Jaeheon Jeong, Adrian Moga, and Koray One
CENG 95-24	Maximum Throughput and the Maximum Balanced Throughput of Mobile Slotted ALOHA Networks by Te-Kai Liu and John A. Silvester
CENG 95-25	RT-Level Power Analysis Using Information Theoretic Measures by Diana Marculescu, Radu Marculescu, and Massoud Pedram
CENG 95-26	SPEED DMON: Cache Coherence on an Optical Multi-channel Interconnect Architecture by Joon-Ho Ha and Timothy M. Pinkston
CENG 95-27	PLA Minimization for Low Power VLSI Designs by S. Iman. C.Y Tsui and M. Pedram
CENG 95-28	Computing Network DCs and Function Minimization Targeting Low Power by Sasan Iman and Massoud Pedram

1994 Tech Reports
CENG 94-01	Formal Verification of Complex Coherence Protocols Using Symbolic State Models by Fong Pong and Michel Dubois
CENG 94-02	Test Embedding With Discrete Logarithms by Mody Lempel, Sandeep K. Gupta and Melvin A. Breuer
CENG 94-03	Unifed System Construction (USC) Tools by Alice Parker
CENG 94-04	Clock Grouping: A Low Cost DFT Methodology for Delay Testing by Wen-Chang Fang and Sandeep K. Gupta
CENG 94-05	Logic Leve Power Estimation Considering Spatiotemporal Correlations by Logic Leve Power Estimation Considering Spatiotemporal Correlations
CENG 94-06	Multi-Level Network Optimization Targeting Low Power by S. Iman and M. Pedram
CENG 94-07	Low Power State Assignment Targeting Two-and Multi-Level Logic Implementations by C-Y Tsui, C-A Chen, M. Pedram. And A.M. Despain
CENG 94-08	Random Pattern Testable Logic Synthesis by Chen-Huan Chiang and Sandeep K. Gupta
CENG 94-09	A Binding Environment for Processing Logic prorams on Large-Scale Parallel Architectures by Hiecheol Kim and Jean-Luc Gaudiot
CENG 94-10	The NDF Model: Processing Logic Programs on Large-Scale Parallel Architectures by Hiecheol Kim and Jean-Luc Gaudiot
CENG 94-11	A Design System To Support Built-In Self-Test of VLSI Circuits Using Bilbo-Oriented test Methodologies by Sen-Pin Lin
CENG 94-12	Zero-Aliasing for Modeled Faults by Mody Lempel and Sandeep K. Gupta
CENG 94-13	Recombination, Selection, and the Genetic Construction of Computer Programs by Walter Alden Tackett
CENG 94-14	Jitter at an ATM Multiplexer in The Presence of Correlated Traffic by Ram Krishnan, John A. Silvester and C. S. Raghavendra
CENG 94-15	The U.S.C Multiprocessor TestBed Project: Project Overview by Michel Dubois, L. Barroso, S. Iman, J. Jeong, k. Oner and K. Ramamurthy
CENG 94-16	Functional Prograaming and Fine-Grain Multithreading for High-Performance Parallel Computing by Chihyun Kim
CENG 94-17	System-Level Design Techniques and Tools for Synthesis of Application-Specific Digital Systems by Chih-Tung Chen
CENG 94-18	A Methodology and Design Tools to Support System-Leel VLSI Design by Kayhan Kucukcakar and Alice C. Parker
CENG 94-19	Approximate Performance models of Multimedia Communications Over Fast Packet-Switched Networks by Stanley Shiouming Wang
CENG 94-20	High-Level Synthesis of Memory-Intensive Application-Specific Systems by Pravil Gupta
CENG 94-21	An Integrated Test Controller Synthesis System by Debaditya Mukherjee
CENG 94-22	A Comparative Study of The Programmability of a Signal Processing Application in an MIMD and an SIMD Multiprocessor by Dae-Kyun Yoon and Jean-Luc Gaudiot
CENG 94-23	DISHA: An Efficient, Fully Adaptive Deadlock Recovery Scheme by Anjan K.V. and Timothy Mark Pinkston
CENG 94-24	D-BMAP Models for Performance Evaluation of ATM Networks by John A. Silvester, Nelson L.S. Fonseca and Stanely S. Wang
CENG 94-25	Queueing Network Models for Multiple Class Broadband Integrated Services Digital Networks by Nelson Luis Saldanha da Fonseca
CENG 94-26	Pseudo-Exhaustive Built-In Self-Test System for Logic Circuits by Rajagopalan Srinivasan
CENG 94-27	Factored Edge-Valued Binary Decision Diagrams and Their Application to Matrix Representation and Manipulation by Paul Tafertshofer and Massoud Pedram
CENG 94-28	A Specification of The Array Semantics for Sisal 2.0 by Yung-Syau Chen and Jean-Luc Gaudiot
CENG 94-29	An Analytical Model for Multi-group Slotted ALOHA With Capture by Te-Kai Liu, John A. Silvester and Andreas Polydoros
CENG 94-30	Performance Evaluation of R-ALOHA in Distributed Packet Radio Networks with Hard Real-Time Communications by Te-Kai Liu, John A. Silvester and Andreas Polydoros
CENG 94-31	A General Performance Model for Mobile Slotted ALOHA Networks with Capture by Te-Kai Liu, John A. Silvester and Andreas Polydoros
CENG 94-32
CENG 94-33	Scan Chaining and Test Scheduling in an Integrated Scan Design System by Sridhar Narayanan
CENG 94-34	A Practical BIST TPG Design Methodology by Chih-Ang Chen and Sandeep K. Gupta
CENG 94-35	Constructing Minimal Spanning Trees with Bounded Path Length by Iksoo pyo, Jaewon Oh and Massoud Pedram
CENG 94-36	An Exact Framework for Post-Layout Timing Correction by Hirendu Vaishnav and Massoud Pedram
CENG 94-37	Built-in Self-Test for Modeled Faults by Mody Lempel
CENG 94-38	Data-Flow Assembly Lanugage by Moez Ayed and Jean-Luc Gaudiot

1993 Tech Reports
CENG 93-01	A Direct Array Handling Technique for Non-strict and Parallel Accesses in a Multithreaded Architecture by Chinhyun Kim and Jean-Luc Gaudiot
CENG 93-02	The Detection and Elimination of Useless Misses in Multiprocessors by Michel Dubois, Jonas Skeppstedt, Luvio Ricciulli, Krishnan Ramamurthy, and Per Stenstrom
CENG 93-03	Estimating the Loss Probability in a Multiplexer Loaded with Multipriority MMPP Streams by Nelson L.S. Fonseca and John A. Silvester
CENG 93-04	Scalable Data Parallel Implementatons of object Recognition using Geometric Hashing by A. Khokhar, H. Kim, V. Prasanna, and C. Wang
CENG 93-05	A Discrete-Time Performance Model for Integrated Services ATM Multiplexers by Shiouming Stanley Wang and John A. Silvester
CENG 93-06	Synthesis of Application-specific Multiprocessor Systems by Shiouming Stanley Wang and John A. Silvester
CENG 93-07	HISS: A Prototype Program for Hierarchical Storage Synthesis by Pravil Gupta and Alice Parker
CENG 93-08	An Efficient Partitioning Strategy for Pseudo-exhaustive Testing by R. Srinivasan, S. Gupta, and M. Breuer
CENG 93-09
CENG 93-10	FGMaps: Mapping for FPGAs using Function Decomposition by Yung-Te Lai, Kuo-Rueih R. Pan and Massoud Pedram
CENG 93-11	FGILP: An Integer Linear Program Solver Based on Function Graphs by Yung-Te Lai, Massoud Pedram and Sarma B.K. Vrudhula
CENG 93-12	Efficient Estimation of Dynamic Power Dissipation by Chi-Ying Tsui, Massoud Pedram and Alvin M. Despain
CENG 93-13	Architecture and Routability Analysis for Row-Based FPGAs. by Massoud Pedram, B. Nobandegani, and Bryan T. Press
CENG 97-14	Efficient Symbolic Simulation under the Extended Bounded Delay Model for Transition Mode Timing Analysis by Chihshun Ding and Massoud Pedram
CENG 93-15	Wire Delay Estimation by Pravil Gupta and Alice Parker
CENG 93-16	PLA Delay Estmation by Pravil Gupta and Alice Parker
CENG 93-17	Performance Analysis of Four Memory Consistency Models for Multithreaded Multiprocessors by Yong-Kim Chong and Kai Hwang
CENG 93-18	Hardwired Barriers for Fast Synchronization of Concurrent Processes on Scalable Multiprocessors by Shisheng Shang and Kai Hwang
CENG 93-19	Multicoloring of Grid-Structured PDE Solvers for Parallel Execution on Multiprocessors by H.C. Wang and Kai Hwang
CENG 93-20	Data Prefetching Effects on the Performance of Multithreaded Multiprocessors by Weighua Mao, Kai Hwang, and Rafeal H. Saavedra
CENG 93-21	Automatic Resolution of Pipeline Hazards in Pipeline Synthesis of Instruction Set Processors by Ing-Jer Huang and Alvin M. Despain
CENG 93-22	Advanced Silicon Compiler in Prolog by Iksoo Pyo, Ching-long Su, Ing-jer Huang, Ricky Pan, Youngseon Koh, Hsu-tsun Chen, Gino Cheng, Chi-ying Tsui, and Alvin M. Despain
CENG 93-23	Correctness of a Directory-Based Cache Coherence Protocol: Early Experience by Fong Pong and Michel Dubois
CENG 93-24	BEST: Behavioral Area-Delay Estimator by Kayhan Kucukcakar and Alice C. Parker
CENG 93-25	Data-Driven and Multithreaded Architectures by Jean-Luc Gaudiot and Chinhyun Kim
CENG 93-26	A Symbolic Approach for Checking Functional and Timing by Chih-Tung Chen and Alice C. Parker
CENG 93-27
CENG 93-28	Hardware/Software Tradeoffs in ADAM by Jagannath Raghavendra and Alice Parker
CENG 93-29	Concurrent High-Level Synthesis with Floorplanning by Jen-Pin Weng
CENG 93-30	Loss Performance & Queue Length Statistics for Multimedia Communication Systems by Shiouming Stanley Wang and John A. Silvester
CENG 93-31	Edge-Valued Binary-Decision Diagrams: Theory and Applications by Yung-Te Lai, Massoud Pedram, and Sastry, Vrudhula
CENG 93-32	Unified System Construction by Alice C. Parker, Chih-Tung Chen & Pravil Gupta
CENG 93-33	A Low Cost BIST Methodology & Associated Novel Test Pattern Generator by Sen Pin Lin, Sandeep K. Gupta and Melvin A. Breuer
CENG 93-34	BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms by Chih-Ang Chen and Sandeep K. Gupta
CENG 93-35	Modelling the Output Process of an ATM Multiplexer with Markov Modulated Arrivals by Nelson Fonseca and John Silvester
CENG 93-36	Estimating End-to-End Delay in ATM Virtual Paths by Estimating End-to-End Delay in ATM Virtual Paths
CENG 93-37	High Level Interprocess Communication Primitives For A Prolog to C-Parallel Translator by Amaury de Cazanove
CENG 93-38	ProPart: A Process-Level Behavioral Partitioner by Chih-Tung Chen and Alice C. Parker
CENG 93-39	SMASH: A Program for Scheduling Memory-Intensive Application Specific Hardware by Pravil Gupta and Alice Parker
CENG 93-40	Fuzzy Communications, Etc by Chien-Ming Cheng and Kai Hwang
CENG 93-41	Compiler-Directed etc. by Chien-Ming Cheng and Kai Hwang
CENG 93-42	Performance Results of The NAS Parallel Benchmarks in SISAL by Hung-Yu Tseng and Jean-Luc Gaudiot
CENG 93-43	Exact & Approximate Methods for Calculating and Transition Probabilities in FSM's by CH-Ying Tsui, Massoud Pedram, Alvin Despain
CENG 93-44	Reduce Power Consumption of a High Performance Processor Through Gray Code Addressing by Ching-Long Su, Chi-Young Tsui, Alvin M. Despain
CENG 93-45	Cold Scheduling: Schedule Instructions for Less Bit Switches by Ching-Long Su and Alvin M. Despain
CENG 93-46	Branch with Masked Squashing in a Superpipelined Prolog Processor by Ching-Long Su and Alvin M. Despain
CENG 93-47	Logic Verification and Synthesis using Function Graphs by Yung-Te Lai

1992 Tech Reports
CENG 92-01	Matching Algorithms and Arichitecture in Hierarchical Shared-Memory Multiprocessor (HSM) Systems by Ashfaq Khokhar and Michel Dubois
CENG 92-02	Synthesis of Interconnection Structures for Multi-Chip Designs by Yung-Hua Hung and Alice Parker
CENG 92-03	CSG: Control Path Synthesis in the ADAM System by Jen-Pin Weng and Alice Parker
CENG 92-04	SWiTEST: Program Organization and Manual by Kuen-Jong Lee and Melvin A. Breuer
CENG 92-05	Towards Synthesizing Memory Architecture for Applications- Specific Systems by Pravil Gupta and Alice C. Parker
CENG 92-06	Reliability Evaluation of Fault-Tolerant Computing Systems and Networks by Meera Balakrishnan
CENG 92-07	A Model for the Performance Analysis of Voice/Data ATM Multiplexers by Shiouming Stanley Wang and John A. Silvester
CENG 92-08	A Multiple Class Buffer Priority Algorithm for the Design of B-ISDN Networks by N. Fonseca and J. A. Silvester
CENG 92-09	Test Pattern Generators for Pseudo Exhaustive Two-Pattern Testing by Sandeep Gupta and Chih-Ang Chen
CENG 92-10	An Approach to Path-Splitting in Multipath Networks by Ram Krishnan and John A. Silvester
CENG 92-11	Delayed Consistency and Its Effects on the Miss Rate of Parallel Programs by Michel Dubois, Jin Chin Wang, Luiz, A. Barroso, Kangwoo Lee and Yung-Syau Chen
CENG 92-12	Scalability Problems in Multiprocessors with Private Caches by Michael Dubois, Luiz, Barroso, Yung-Syau Chen and Koray Oner
CENG 92-13	Cache Inclusion and Processor Sampling in Multiprocessor simuations by Jacqueline Chame and Michel Dubois
CENG 92-14	Improving the Performance of Data Caches in Systems with Large Miss Latencies by Koray Oner and Michel Dubois
CENG 92-15	Alphabetic Fanout Optimization by Hirendu Vaishnav and Massoud Pedram
CENG 92-16	Power-Efficient Technology Decomposition and Mapping by Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
CENG 92-17	BDD-Based Logic Decomposition: Theory and Practice by Yung-Te Lai, Massoud Pedram, Sarma Sastry
CENG 92-18	Hardware/Software Resolutions for Pipeline Hazards in Instruction Set Processors by Ing-Jer Huang and Alvin Despain
CENG 92-19	The Performance of Cache-Coherent Ring-based Multiprocessors by Luiz Andre Barroso and Michel Dubois
CENG 92-20	The Verification of Cache, Coherence Protocols by Fong Pong and Michel Dubois
CENG 92-21	A Fast Performance Model for Real-Time Multimedia Communications by Shiouming Stanley Wang and John A. Silvester
CENG 92-22	High-Level Synthesis with Pin Constraints for Multiple-Chip Designs by Yung-Hua Hung
CENG 92-23	Dream Machine- A Platform for Efficient Implementation of Neural Networks with Abitrarly Complex by Soheil Shams
CENG 92-24	2D Object Recognition by Adaptive Feature Extraction and Dynamical Link Graph Matching by Kenneth Flaton
CENG 92-25	BIST Test Pattern Generators for Two-Pattern Pseudo-Exhaustive testing by Sandeep K. Gupta and Chih-Ang Chen

1991 Tech Reports
CENG 91-01	Unified System Construction by Kayhan Kucukcakar, Alice C. Parker, Shiv Prakash, Jen-Pin Weng
CENG 91-02	Maximal Diagosis for Wiring Networks by Jung-Cheun Lien and Melvin Breuer
CENG 91-03	A Snooping Cache Coherence Protocol for a Ring Connected Multipro by Luiz A. Barroso and Michel Dubois
CENG 91-04	Stochastic Testability Analysis in Homogeneous Circuits by Amitava Majumdar and Sarma Sastry
CENG 91-05	Neural Network Vision Integration Through Cooperative Learning on a Massively Parallel Computer by Scott Toborg and Kai Hwang
CENG 91-06	Fast Synchronization of Large Multiprocessors Using Wired-NOR Barriers and Counting Semaphores by Kai Hwang and Shisheng Shang
CENG 91-07	Mapping Multicomputer Communication Patterns onto Multiprocessors as Message Vectors in Shared Memory by Dhabaleswar K. Panda and Kai Hwang
CENG 91-08	Performance Analysis of a Simulated Orthogonal Multiprocessor by Kai Hwang and Chien-Ming Cheng
CENG 91-09	SIESTA 1.0 User's Manual by Rajesh Gupta
CENG 91-10	Advanced Serial Scan Design for Testability by Rajesh Gupta
CENG 91-11	Heuristic Process Migration for Dynamic Load Balancing in a Message-Passing Multicomputer by Kai Hwang and Jian Xu
CENG 91-12	Analytical Modeling of Shared Block Contention in Cache Coherence Protocols by Jin-Chin Wang
CENG 91-13	Numerical Partial Differential Equtaions Solvers on Variable-grain Data-flow Multiprocess systems by Chih-Ming Lin
CENG 91-14	Delayed Consistencey and Its Effects on the Miss Rate of Parallel Programs by Michael Dubois, Jin-Chin Wang, Luiz A. Barros, Kangwoo Lee, Yung-Syau Chen
CENG 91-15	Reconfigurable Networks For Fast Packet Switching Shih-Chian Yang by Shi-Chian Yang
CENG 91-16	Control Path/Data Path Tradeoffs in VLSI Design by Mitchell J. Misnar
CENG 91-17	A Mathematical Programming Model for Synthesis of Multiprocessor systems: Linearization, An example Model, and Some Tradeoff Studies by Shiv Prakash and Alice C. Parker
CENG 91-18	A Systematic Approach for Designing Testable VLSI Circuits by Sen-Pin Lin, Charles A. Nijinda, and Melvin Breuer
CENG 91-19	Design of Hierarchically Testable and Maintainable Systems by Jung-Cheun Lien
CENG 91-20	Synthesis of Optimal 1-Hot Coded On-chip Controllers for BIST Hardware by D. Mukherjee, C. Nijinda, and M. A. Breuer
CENG 91-21	VHDL2DDS: A VHDL Language to DDS Data Structure Translator by Chih-Tung Chen
CENG 91-22	Switch Level Test Generation for CMOS Circuits by Kuen-Jong Lee
CENG 91-23	Parallel Orientation of Polygonal Parts by Viktor Prasanna and Anil Rao
CENG 91-24	Parallel Processing of Production Systems on Data-Flow Multiprocessors by Andrew Sohn
CENG 91-25	Parallel Algorithms For Automating VLSI Physical Design by Ravikumar P. Chennagiri
CENG 91-26	Software Aspects of Bold A System and User's Manual by Jung-Cheun Lien
CENG 91-27	System-Level Synthesis Techniques with Emphasis On Partitioning And Design Planning by Kayhan Kucukcakar
CENG 91-28	Numerical Partial Differential Equations Solvers on Variable-grain Data-flow Multiprocessor Systems by Chih-Ming Lin
CENG 91-29	SOS: Synthesis of Application-Specific Heterogeneous Multiprocessor systems by Shiv Prakash and Alice C. Parker
CENG 91-30	Symbolic Jacobian Inversion for Redundant Manipulators by Carlos L. Luck and Sukhan Lee
CENG 91-31	Emulating a Data-Flow Machine Using a Network of Transputers by Moez Ayed and Jean-Luc Gaudiot

1990 Tech Reports
CENG 90-01	SNAP Controller by Hirendu Vaishnav
CENG 90-02	Algorithm-Driven Performance Simulation of the USC Orthogonal Multiprocessor by Chien-Ming Cheng, Sharad Mahrotra, Michael Dubois, Kai Hwang
CENG 90-03	Architectural Design of the USC Orthogonal Multiprocessor by K. Hwang, D. K. Panda, S. Rao and H. Nais
CENG 90-04	The USC Orthogonal Multiprocessor for Image Processing with Neural Networks by K. Hwang D. K Panda, N. Haddadi and R. Chellappa
CENG 90-05	A Decoupled Graph/Computation Architecture with Variable Resolution Actors by P. Evripidou and Jean-Luc Gaudiot
CENG 90-06	Dynamic Routing and Congestion Control for Multi-Class Virtual Circuit Networks by A. A. Eonomides, P. A. Ioannou and J A. Silvester
CENG 90-07	Evaluating Optimizing Transformations of Behavioral Descriptions by Rajiv Jain and Alice Parker
CENG 90-08	Test Generation for the JPL Viterbi Decoder Chip by M.A Breuer, Margaret Driscoll, Rajesh Gupta, Rajiv Gupta, Shen Lin and Rajagopalan Srinivasan
CENG 90-09	Assigning Signa flow Directions to MOS Transistors by Lee, Gupta, Breuer
CENG 90-10	Test-Efficiency Analysis of Random Self-test of Sequential Circuits by Sastry and Majumdar
CENG 90-11	Stochastic Characterization of Controllability ingeneral NAND and AND Trees by Amita Majumdar and Sharma Sastry
CENG 90-12
CENG 90-13	Efficient Testing of Acyclic Structures in Partial Scan Designs by Rajesh Gupta and Melvin A. Breuer
CENG 90-14	A Module Maintenance Controller Prototype by Jung-Chuen Lien
CENG 90-15	Asynchronous Iterative Algorithms for Problems with Discrete Data by Aydin Uresin
CENG 90-16	Priority Load Sharing: An Approach Using Stackelberg Games by A. A. Economedies and John Silvester
CENG 90-17	VYUHA: A Detailed Router for Multiple Routing Models by C.P. RaviKumar and S. Sastry
CENG 90-18	Virtual Address Caches by Michael Cekleov, Michael Dubois, Jun-Chin Wang, Faye A. Briggs
CENG 90-19	A Methodology for Partitioning and Hierarchical Reorganization of Ssequential Circuits for DFT and BIST by Rajiv Gupta, Rajagopalan Srinivasan and Melvin Breuer
CENG 90-20	On Optimal and Practical Routing Methods for a Massive Data Movement Operation on Hypercubes by Rajendra V. Boppana and C. S. Raghavendra
CENG 90-21	Delayed Consistency Protocols by Michael Dubois
CENG 90-22	Improving Structure Handling and Recursive Function Calls in the USC Occamflow Translator by Jean-Pierre Abello
CENG 90-23	Macro Data-Flow Simulator Display Interface by Olivier Tardieu
CENG 90-24	The Effects of Physical Design Characteristics on the Quality of Synthesized Designs by Alice C. Parker, Jen-Pin Weng, Pravil Gupta and Agha Hussain
CENG 90-25	Synthesis of Application-Specific Multiprocessor Architectures byShiv Prakash and Alice C. Parker
CENG 90-26	CHOP: A Constraint-Driven System- Level Partitioner by Kayhan Kucukcakar and Alice .C Parker
CENG 90-27	3D Scheduling: High Level Synthesis with Floorplanning by Jen-Pin Weng and Alice C. Parker
CENG 90-28	Reconfigurable fault Tolerant Networks for Fast Packet Switching by Shih-Chian Yang and John A. Silvester
CENG 90-29	The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve by Alice Parker, Pravil Gupta and Agha Hussain
CENG 90-30	Flexible, Fault-Tolerant Routing Criteria for Circuit-Switched Hypercubes by Ge-Ming Chiu, Suresh Chalasani and C.S. Raghavandra
CENG 90-31	BAD: Behavioral Area-Delay Predictor by Kayhan Kucukcakar and Alice C. Parker
CENG 90-32	The Synthesis of Control-Dominated Application Specific Integrated Circuits Using Global Based Design Management by Sally Hayati